Program method of flash memory device

ABSTRACT

In a program method of a flash memory device where memory cells within a string are turned on to electrically connect channel regions, all of the channel regions within a second string are precharged uniformly by applying a ground voltage to a first bit line connected to a first string including to-be-programmed cells and a program-inhibited voltage to a second bit line connected to the second string including program-inhibited cells. If a program operation is executed, channel boosting occurs in the channel regions within the second string including the program-inhibited cells. Accordingly, a channel boosting potential can be increased and a program disturbance phenomenon, in which the threshold voltage of program-inhibited cells is changed, can be prevented.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority to Korean patent applicationnumber 10-2007-91529, filed on Sep. 10, 2007, which is incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a program method of a flash memorydevice and, more particularly, to a program method of a flash memorydevice, which minimizes program disturbance during a program operation.

A flash memory device is a type of non-volatile memory device in whichstored data is not erased when a power supply is removed.

Data can be stored in or deleted from a flash memory device through aprogram operation or an erase operation. The flash memory device can beclassified as a NOR type or a NAND type depending on the shape of amemory cell array. The NAND flash memory device is advantageous in thatit can have a high level of integration compared with the NOR flashmemory device. A memory cell array of the NAND flash memory device and aprogram operation method are described below.

FIG. 1 is a circuit diagram illustrating a cell array of a conventionalNAND flash memory device and a program operation method thereof.

Referring to FIG. 1, the cell array of the NAND flash memory deviceincludes a plurality of memory cell blocks. Each cell block includes aplurality of cell strings (only two cell strings ST1 and ST2 areillustrated for convenience). The cell strings are respectivelyconnected to bit lines BL1 and BL2. In more detail, the cell string ST1has a structure in which a drain select transistor DST, a plurality ofmemory cells CA0 to CAn, and a source select transistor SST areconnected in series. The drain select transistor DST, included in eachcell string, has a drain connected to a corresponding bit line BL1, andthe source select transistor SST, included in each cell string, has asource connected to a common source line CSL. The drain selecttransistors DST, included in the respective cell strings ST1 and ST2,have gates connected to each other, thereby forming a drain select lineDSL. The source select transistors SST, included in the respective cellstrings ST1 and ST2, have gates connected to each other, thereby forminga source select line SSL. The memory cells CA0 to CAn and CB0 to CBnhave gates connected to each other, thereby forming word lines WL0 toWLn. The memory cells CAk and CBk, which share a word line (for example,WLk), are classified on a per page (PG) basis.

A program operation of the NAND flash memory device is executed on a perpage basis. During the program operation, the drain select line DSL issupplied with a drain select voltage, for example a power supply voltageVcc, and the source select line SSL is supplied with a ground voltage. Aprogram voltage is applied to a selected word line (for example WLk),and a pass voltage is applied to the remaining word lines. Under theabove conditions, the program operation of memory cells sharing theselected word line WLk is executed.

The threshold voltage of a memory cell is raised by the programoperation, and a logical value of stored data is classified according tothe changed threshold voltage of the memory cell.

Although both the memory cells CAk and CBk sharing the selected wordline WLk can be programmed, under certain circumstances both the memorycells CAk and CBk sharing the selected word line WLk may not beprogrammed according to stored data. Different voltages are applied tobit lines connected to a corresponding string depending on which one ofa to-be-programmed cell and a not-to-be-programmed cell is included inthe string (a cell in which an erase state or a previous state is to bemaintained). A cell that should not be programmed is hereinafterreferred to as a “program-inhibited cell.”

Specifically, a ground voltage is applied to a bit line BL1 connected tothe string ST1, including a to-be-programmed cell (for example, CAk).The ground voltage causes the voltage level of a channel region withinthe string ST1 to drop to the level of the ground voltage. Consequently,a high potential is maintained between the word line WLk and the channelregion, and electrons are injected from the channel region to a floatinggate of the memory cell CAk by F-N tunneling, so that the thresholdvoltage of the memory cell is raised. Accordingly, the program operationis executed.

A program-inhibited voltage (for example, a power supply voltage Vcc)for channel boosting is applied to a bit line BL2 connected to thestring ST2, including a program-inhibited cell (for example, CBk). Thepower supply voltage causes the channel region within the string ST2 tobe precharged to a level higher than OV (Vcc-Vth, where V is thethreshold voltage of the drain select transistor). If the channel regionis precharged, the drain select transistor DST is turned off and thechannel region of the string ST2, including the program-inhibited cellCBk, is floated in a precharged state because Vgs (the potential betweenthe gate and the source) of the drain select transistor DST is notgreater than the threshold voltage. If a pass voltage and a programvoltage are then applied to the word lines WL0 to WLk, the voltage levelof the channel region is raised higher than that of the power supplyvoltage due to a channel boosting phenomenon. Consequently, thepotential between the word line WLk and the channel region decreases, sothat F-N tunneling is not generated and the threshold voltage of thememory cell is not changed. Accordingly, the program-inhibited cell doesnot experience the program operation. In this case, the greater thedifference between the voltage applied to the word line and the voltageof the channel region, the better the channel boosting characteristic.

A program method of storing 2-bit data or more in one memory cell hasrecently been developed. In order to store 2-bit data in one memorycell, threshold voltage distributions of the memory cell must beclassified into four types and at least two program operations must beexecuted on one memory cell.

In the event that data stored in a memory cell of an erase state isdefined as ‘11’, a first program operation for changing a lower bit to‘0’ and a second program operation for changing an upper bit to ‘0’ mustbe executed. The first and second program operations are generallyperformed sequentially from the first word line WL0 to the last wordline WLn.

When the program operation of the memory cells CAk and CBk, sharing ak^(th) word line WLk, is executed according to the above method, thememory cells CB0 to CBk−1 disposed on the source select transistor (SST)side have already experienced the program operation. The cells areclassified into a program state or an erase state according to storeddata. A memory cell CBk+1 disposed on the drain select transistor (DST)side has not experienced the program operation, and is thereforemaintained at an erase state. If a larger number of programmed cellsexist on the source select transistor (SST) side, the potential betweenthe word line and the channel region decreases due to electrons injectedinto the floating gate, so that a weak channel boosting phenomenon mayoccur. Thus, if the number of programmed cells varies for every string,channel boosting occurs with different intensities, which may result ina changed program characteristic. This phenomenon may happen not only inthe program operation for storing 2-bit data, but also in a programmethod of storing 1-bit data.

In order to prevent this phenomenon, the program operation can beperformed by using an erase area self-boosting (EASB) method ofgenerating channel boosting only in a channel region of memory cells,which are maintained at an erase state while being placed on the drainselect transistor (DST) side in the selected word line WLk.Alternatively, the program operation can be performed by using a localself-boosting (LSB) method of generating channel boosting only in achannel region of memory cells, which share the selected word line WLkby turning off the memory cells WLk−1 and WLk+1 adjacent to the selectedword line WLk.

The program operation of the EASB method or the LSB method can have agood effect when memory cells disposed between the selected word lineWLk and the drain select line DSL are in an erase state. However, inorder to minimize an interference phenomenon in which the thresholdvoltage of neighboring memory cells is changed during a programoperation of memory cells sharing a selected word line, the sequence ofthe first and second program operations or the sequence of word lines ischanged. In this case, since programmed cells may exist between theselected word line WLk and the drain select line DSL, it is difficult toobtain good program characteristics even with the program operation ofthe EASB method or the LSB method. In particular, in the programoperation of the LSB method, if a program voltage is applied, hotelectrons generated from junction regions of memory cells that areturned off on both sides of the selected word line WLk are injected intothe floating gate of the program-inhibited cell CBk according to theprogram voltage, resulting in a program disturbance phenomenon in whichthe threshold voltage rises.

Consequently, in order to obtain good program characteristics whilepreventing program disturbance, it is very important to control theoccurrence of channel boosting within a string includingprogram-inhibited cells.

BRIEF SUMMARY OF THE INVENTION

According to the present invention, in the state where all memory cellswithin a string are turned on to electrically connect channel regions,all of the channel regions within a second string are prechargeduniformly by applying a ground voltage to a first bit line connected toa first string including to-be-programmed cells and a program-inhibitedvoltage to a second bit line connected to the second string includingprogram-inhibited cells. If a program operation is executed, channelboosting occurs in the channel regions within the second stringincluding the program-inhibited cells. Accordingly, a channel boostingpotential can be increased and a program disturbance phenomenon in whichthe threshold voltage of program-inhibited cells is changed can beprevented.

A program method of a flash memory device according to a firstembodiment of the present invention includes providing a memory devicecomprising a drain select line, a source select line, and word lines,and having a string connected between a bit line and a common sourceline; applying a program-inhibited voltage in a state where channelregions within the string are not electrically connected to the bitline; applying a pass voltage to the word lines; applying a drain selectvoltage to the drain select line; and executing a program operation byapplying a program voltage higher than the pass voltage to a selectedone of the word lines.

A program method of a flash memory device according to a secondembodiment of the present invention includes providing a memory devicecomprising a drain select line, a source select line, and word lines,and having strings respectively connected between bit lines and a commonsource line; in a state where channel regions within the string are notelectrically connected to the bit lines, applying a ground voltage to afirst bit line connected to a first string including a to-be programmedmemory cell and applying a program-inhibited voltage to a second bitline connected to a second string including a program-inhibited cell;applying a pass voltage to the word lines; applying a drain selectvoltage to the drain select line; and executing a program operation byapplying a program voltage higher than the pass voltage to a selectedone of the word lines.

Memory cells that share the word lines may be all turned on according tothe pass voltage irrespective of a program state. During execution ofthe program operation, a level of the pass voltage applied to theselected word line may rise to a level of the program voltage. A drainselect transistor included in the first string may be turned onaccording to the drain select voltage, so that channel regions withinthe first string may be electrically connected to the first bit line.

A program method of a flash memory device according to a thirdembodiment of the present invention includes providing a memory devicecomprising a drain select line, a source select line, and word lines,and having a string connected between a bit line and a common sourceline; applying a program-inhibited voltage to the bit line in a floatingstate where channel regions within the string are not electricallyconnected to the bit line; electrically connecting the channel regionsin a state where the channel regions are not electrically connected tothe bit line; applying a drain select voltage to the drain select line;and executing a program operation by applying a program voltage higherthan a pass voltage to a selected one of the word lines.

The channel regions may be connected according to the pass voltageapplied to each of the word lines. When the channel regions areconnected according to the pass voltage, a channel boosting phenomenonmay be generated and a voltage of the channel regions may rise. Theprogram-inhibited voltage may be applied earlier than the pass voltage,the pass voltage may be applied earlier than the program-inhibitedvoltage, or the pass voltage and the program-inhibited voltage may beapplied at the same time. The drain select voltage may be applied afterthe program-inhibited voltage and the pass voltage are applied.

A program method of a flash memory device according to a fourthembodiment of the present invention includes providing a memory devicecomprising a drain select line, a source select line, and word lines,and having strings respectively connected between bit lines and a commonsource line; in a floating state where channel regions within the stringare not electrically connected to the bit lines, applying a groundvoltage to a first bit line connected to a first string including ato-be programmed memory cell and applying a program-inhibited voltage toa second bit line connected to a second string including aprogram-inhibited cell; in a state where the channel regions are notconnected to the bit lines, electrically connecting first channelregions of memory cells, included in the first string, and secondchannel regions of memory cells, included in the second string,respectively; in a state where the first and second channel regions areconnected to each other, electrically connecting the first channelregions to the first bit line; and executing a program operation so thata threshold voltage of the to-be programmed memory cell rises.

The first channel regions may be connected to each other according to apass voltage applied to each of the word lines, and the second channelregions may be connected to each other according to the pass voltageapplied to each of the word lines. Since a channel boosting phenomenonis generated in each of the first and second channel regions by the passvoltage, a voltage of the first and second channel regions may rise. Thefirst channel regions may be connected to the first bit line as a drainselect transistor of the first string is turned on according to a drainselect voltage applied to the drain select line. The drain selectvoltage may have the same level as that of the program-inhibitedvoltage. The program-inhibited voltage may be applied before the firstand second channel regions are connected to each other, theprogram-inhibited voltage may be applied after the first and secondchannel regions are connected to each other, or the first and secondchannel regions may be connected to each other at the same time when theprogram-inhibited voltage is applied. After the first and second channelregions are connected to each other and the program-inhibited voltage isapplied, the first channel regions may be electrically connected to thefirst bit line. In the application of the program-inhibited voltage, asource select voltage for turning off a source select transistor may beapplied to the source select line, and a positive voltage may be appliedto a common source line.

A program method of a flash memory device according to a fifthembodiment of the present invention includes providing a memory devicecomprising a drain select line, a source select line, and word lines,and having a string connected between a bit line and a common sourceline; applying a ground voltage to the bit line and a first voltage tothe drain select line; applying a second voltage to the word lines sothat memory cells are turned on; applying a pass voltage higher than thesecond voltage to the word lines while applying a program-inhibitedvoltage to the bit line; and executing a program operation by applying aprogram voltage higher than the pass voltage to a selected one of theword lines.

A program method of a flash memory device according to a sixthembodiment of the present invention includes providing a memory devicecomprising a drain select line, a source select line, and word lines,and having strings respectively connected between bit lines and a commonsource line; applying a ground voltage to the bit lines and a firstvoltage to the drain select line; applying a second voltage to the wordlines so that memory cells are turned on; applying a pass voltage higherthan the second voltage to the word lines, a ground voltage to a firstbit line connected to a first string including a to-be programmed memorycell, and a program-inhibited voltage to a second bit line connected toa second string including a program-inhibited cell; and executing aprogram operation by applying a program voltage higher than the passvoltage to a selected one of the word lines.

The memory cells may be all turned on according to the second voltageirrespective of a program state or an erase state. During execution ofthe program operation, a level of the pass voltage applied to theselected word line may rise to a level of the program voltage.

A drain select transistor included in the first string may be turned onaccording to the first voltage applied to the drain select line, so thatchannel regions within the first string may be electrically connected tothe first bit line. Channel regions within the string may beelectrically connected to one another according to the second voltage.The channel regions within the string may be disposed in a semiconductorsubstrate between the source select line and the drain select line, orin a semiconductor substrate under the word lines.

A program method of a flash memory device according to a seventhembodiment of the present invention includes providing a memory devicecomprising a drain select line, a source select line, and word lines,and having a string connected between a bit line and a common sourceline; applying a ground voltage to the bit line and a first voltage tothe drain select line; electrically connecting channel regions withinthe string; generating a channel boosting phenomenon in the channelregions, thereby raising a potential of the channel regions; andexecuting a program operation by applying a program voltage to aselected one of the word lines.

The channel regions may be connected to one another when memory cellsthat share the word lines are turned on according to a second voltageapplied to the word lines. The potential of the channel regions may risein proportion to a value in which a voltage applied to the word linesrises as a drain select transistor that shares the drain select line isturned off according to a program-inhibited voltage applied to the bitline and the channel regions enter a floating state.

A program method of a flash memory device according to an eighthembodiment of the present invention includes providing a memory devicecomprising a drain select line, a source select line, and word lines,and having strings connected between bit lines and a common source line;applying a ground voltage to the bit lines and a first voltage to thedrain select line; connecting first channel regions of a first string ofthe strings, which includes a to-be programmed memory cell, and secondchannel regions of a second string of the strings, which includes aprogram-inhibited cell; applying a ground voltage to the first channelregions of the first string and generating a channel boosting phenomenonin the second channel regions of the second string, thereby raising apotential of the second channel regions; and executing a programoperation by applying a program voltage to a selected one of the wordlines.

Memory cells that share the word lines may be turned on according to asecond voltage applied to the word lines, so that the first channelregions and the second channel regions are connected to each other.While a drain select transistor of the first string that shares thedrain select line is turned on, the first channel regions may beelectrically connected to the first bit line, so that the ground voltageis applied to the first channel regions. The potential of the channelregions may rise in proportion to a value in which a voltage applied tothe word lines rises as a drain select transistor of the second stringthat shares the drain select line is turned off according to aprogram-inhibited voltage applied to the second bit line and the channelregions enter a floating state. During the application of the firstvoltage to the drain select line, a source select voltage may be appliedto the source select line so that a source select transistor is turnedoff and a positive voltage is applied to a common source line. Thechannel regions within the string may be disposed in a semiconductorsubstrate between the source select line and the drain select line.

According to the present invention, in the state where all of the memorycells within a string are turned on, a program-inhibited voltage isapplied to a bit line. Accordingly, all of the channel regions withinthe string can be precharged uniformly.

Further, channel boosting is generated in the state where the channelregions are precharged uniformly. Accordingly, a channel boostingpotential can be increased and the occurrence of program disturbance canbe minimized.

The present invention can also be applied to a case where the sequenceof program operations or word lines is changed in order to prevent avariation in the threshold voltage of neighboring cells due to aninterference phenomenon during a program operation. In particular, thepresent invention can also be applied to a case where memory cellslocated between a selected word line and a drain select line have beenprogrammed.

Further, channel boosting is generated not only in a channel regionwithin a string, but also in the entire channel region. It is thereforepossible to prevent the threshold voltage of program-inhibited cellsfrom being changed due to hot electrons when channel boosting occurs insome regions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating a cell array of a conventionalNAND flash memory device and a program operation method thereof;

FIG. 2 is a circuit diagram illustrating a program method of a flashmemory device according to an embodiment of the present invention;

FIG. 3 is a waveform illustrating a program method of a flash memorydevice according to a first embodiment of the present invention;

FIG. 4 is a cross-sectional view of memory cells CAk, CBk that share ak^(th) word line in the circuit diagram of FIG. 2;

FIGS. 5A to 5D are cross-sectional views of a string in the circuitdiagram of FIG. 2;

FIG. 6 is a waveform illustrating a program method of a flash memorydevice according to a second embodiment of the present invention;

FIG. 7 is a waveform illustrating a program method of a flash memorydevice according to a third embodiment of the present invention; and

FIG. 8 is a waveform illustrating a program method of a flash memorydevice according to a fourth embodiment of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Specific embodiments according to the present invention will bedescribed with reference to the accompanying drawings.

FIG. 2 is a circuit diagram illustrating a program method of a flashmemory device according to an embodiment of the present invention. FIG.3 is a waveform illustrating a program method of a flash memory deviceaccording to a first embodiment of the present invention. FIG. 4 is across-sectional view of memory cells CAk, CBk that share a k^(th) wordline in the circuit diagram of FIG. 2.

Referring to FIG. 2, the flash memory device according to an embodimentof the present invention includes a memory cell array 210, a voltagegenerator 220, and page buffers 230A and 230B. The memory cell array 210includes a plurality of blocks, each of which includes a plurality ofstrings (only two cell strings ST1 and ST2 are illustrated forconvenience). As shown in FIGS. 4 and 5A, a word line and a select lineinclude tunnel insulating layers 305, a floating gate 307, dielectriclayers 309, and a control gate 311; all of which are stacked over asemiconductor substrate 301. Two select lines SSL and DSL are connectedto the floating gate 307 and the control gate 311 since a hole is formedin the dielectric layer 309. Junction regions 315J are formed in thesemiconductor substrate 301 between the word lines and the select lines.A bit line BL1 is connected to a source 315S formed at one side of acommon source line CSL. A bit line BL2 is connected to a drain 315D ofthe drain select line DSL. The memory cell array 210 has the same memorycell array structure as that of FIG. 1, and a description thereof willbe omitted for simplicity.

Referring back to FIG. 2, the voltage generator 220 supplies operatingvoltages, necessary for a program operation, to the drain select lineDSL, word lines WL0 to WLn, and the source select line SSL. Page buffers230A and 230B are respectively connected to the drains of drain selecttransistors DST included in the strings ST1 and ST2 through the bitlines BL1 and BL2. The page buffers 230A and 230B apply aprogram-inhibited voltage (for example, a power supply voltage) or aground voltage to the bit lines according to externally input data.

A program operation when a memory cell CAk of memory cells CAk and CBk,which share a k^(th) word line WLk, is a to-be-programmed cell and thememory cell CBk is a program-inhibited cell that should be maintained ata previous state, is described below.

Referring to FIGS. 3, 4, and 5A, in a first period T1, aprogram-inhibited voltage or a ground voltage is applied to the bitlines BL1 and BL2 according to externally input data. The ground voltageis applied to the first bit line BL1 connected to the first string ST1including the first memory cell CAk to be programmed, and aprogram-inhibited voltage Vpch is applied to the second bit line BL2connected to the second string ST2 including the second memory cell CBk(that is, a program-inhibited cell). A power supply voltage is appliedto the common source line CSL and the ground voltage is applied to thesource select line SSL. Since the ground voltage is applied to the drainselect line DSL, the program-inhibited voltage Vpch is not transferredto a second channel region 313B within the second string ST2. That is,even if the program-inhibited voltage Vpch is applied, the secondchannel region 313B of the second string ST2 is not precharged.

Referring to FIGS. 3, 4, and 5B, in a second period T2, a pass voltageVpass is applied to the word lines WL0 to WLn so that all of the memorycells CA0 to CAn and CB0 to CBn, which are included in a block selectedat the time of a program operation, are turned on. The pass voltageVpass refers to a voltage, which is applied to turn on memory cellsconnected to an unselected word line during a general program operation.As the pass voltage Vpass is applied to the word lines WL0 to WLn, allof the memory cells CA0 to CAn and CB0 to CBn are turned on, and all ofthe channel regions are electrically connected to the semiconductorsubstrate 301 between the source select line SSL and the drain selectline DSL within each of the strings ST1 and ST2. Since the drain selectline DSL and the source select line SSL are supplied with the groundvoltage and the drain select transistor DST and the source selecttransistor SST are in a turn-off state, the first and second channelregions 313A and 313B of the strings ST1 and ST2 are supplied with thepass voltage Vpass in a floating state. Accordingly, a boostingphenomenon occurs in the strings ST1 and ST2 due to a capacitancecoupling phenomenon, so that the voltage levels of the first and secondchannel regions 313A and 313B rise.

Although programmed cells exist in the second string ST2 including theprogram-inhibited cell CBk, all of the memory cells CB0 to CBn areturned on to connect the channel regions. Thus, after a boostingphenomenon is generated, a uniform potential can be maintained in thesecond channel region 313B within the second string ST2 irrespective ofthe programmed cells.

Referring to FIGS. 3, 4, and 5C, in a third period T3, a drain selectvoltage is applied to the drain select line DSL. The drain selectvoltage applied to the drain select line DSL may have the same level asthat of the program-inhibited voltage applied to the second bit lineBL2. If the drain select voltage is applied to the drain select lineDSL, the drain select transistor DST of the first string ST1 is turnedon and, therefore, the first bit line BL1 applied to the ground voltageis electrically connected to the first channel region 313A of the firststring ST1. Thus, the voltage level of the first channel region 313A ofthe first string ST1 drops to the level of the ground voltage. Althoughthe drain select voltage is applied to the drain select line DSL in thesecond string ST2, the drain select transistor DST is not turned on dueto a difference between Vgs (the potential between the gate and thesource) and Vth (the threshold voltage of the drain select transistor).The second channel region 313B of the second string ST2 is kept at avoltage level, which is raised by a boosting phenomenon. If the boostedvoltage level of the second channel region 313B is lower than theprogram-inhibited voltage, the drain select transistor DST of the secondstring ST2 is turned on and the second channel region of the secondstring ST2 is precharged to a predetermined level (i.e., theprogram-inhibited voltage which is the threshold voltage of the drainselect transistor). The drain select transistor DST is then turned off.

Referring to FIGS. 3, 4, and 5D, in a fourth period T4, a programoperation is performed by applying a program voltage Vpgm to a selectedword line WLk. In the first string ST1, electrons are injected from thefirst channel region 313A to the floating gate 307 of the memory cellCAk due to the potential between the word line WLk of the memory cellCAk and the first channel region 313A, so that the threshold voltagerises. Consequently, the memory cell CAk is programmed.

The program voltage Vpgm is applied in the state where the drain selecttransistor DST of the second string ST2 is turned off and the secondchannel region 313B of the second string ST2 is floated. Thus, aboosting phenomenon occurs in the second channel region 313B of thesecond string ST2 due to the program voltage Vpgm, and the voltage ofthe second channel region 313B rises additionally. As a result, sincethe potential between the word line WLk of the program-inhibited cellCBk and the second channel region 313B further decreases, theprogram-inhibited cell CBk is not programmed and a program disturbancephenomenon is not generated.

After the program voltage Vpgm is applied for a time sufficient toprogram the memory cell CAk, the supply of the program voltage Vpgmapplied for the program operation, the pass voltage Vpass, and the drainselect voltage applied to the drain select line DSL is stopped in theremaining periods. The supply of the program voltage Vpgm, the passvoltage Vpass, and the drain select voltage may be stopped sequentially.Though not shown in the drawing, the supply of the program-inhibitedvoltage Vpch and the voltage of the common source line CSL is alsostopped.

After the program operation is performed, a program verificationoperation for verifying whether the threshold voltage of the memory cellCAk has risen to a target voltage is performed. If, as a result of theverification, the threshold voltage of the memory cell CAk has risen tothe target voltage, the program operation is finished. However, if, as aresult of the verification, the threshold voltage has not risen to thetarget voltage, the program operation is performed again according tothe above method while raising the level of the program voltage Vpgmstep-by-step until the threshold voltage becomes the same as or higherthan the target voltage.

It has been described above that before the drain select voltage isapplied to the drain select line DSL, that is, the channel regionswithin the string are electrically connected to the bit line, theprogram-inhibited voltage is applied to the bit line before the passvoltage. However, the program-inhibited voltage may be applied to thebit line in various ways.

FIG. 6 is a waveform illustrating a program method of a flash memorydevice according to a second embodiment of the present invention.

Referring to FIG. 6, in the program method of the flash memory deviceaccording to the second embodiment of the present patent, before thedrain select voltage is applied to the drain select line DSL, the passvoltage is applied to the word lines WL0 to WLn before theprogram-inhibited voltage. Even in this case, a channel boostingphenomenon described with reference to FIG. 3 can be generateduniformly.

Although it has been described that the program-inhibited voltage isapplied before the drain select voltage, the program-inhibited voltageand the drain select voltage may be applied at the same time.

FIG. 7 is a waveform illustrating a program method of a flash memorydevice according to a third embodiment of the present invention.

Referring to FIG. 7, in the program method of the flash memory deviceaccording to the third embodiment of the present invention, before thedrain select voltage is applied to the drain select line DSL, the passvoltage and the program-inhibited voltage may be applied to the wordlines WL0 to WLn and the bit line, respectively, at the same time. Inthis case, a channel boosting phenomenon described with reference toFIG. 3 can also be generated uniformly.

It has been described above, with reference to FIGS. 6 and 7, that thepass voltage is applied simultaneously with a positive voltage appliedto the common source line CSL. However, the pass voltage may be appliedbefore the positive voltage of the common source line CSL.

FIG. 8 is a waveform illustrating a program method of a flash memorydevice according to a fourth embodiment of the present invention.

Referring to FIGS. 2, 4, and 8, in a first period T1, a first voltagefor turning on the drain select transistor DST is applied to the drainselect line DSL, and a ground voltage is applied to the bit lines BL1and BL2 and the word lines WL0 to WLn. Even though the drain selecttransistor DST is turned on, the channel regions 313A and 313B are notprecharged because the ground voltage is applied to the bit lines BL1and BL2.

The source select voltage of, for example, 0 V may be applied to thesource select line SSL so that the source select transistor SST isturned off. Further, although the source select transistor SST is turnedoff, the leakage current to the common source line CSL can be generated.Accordingly, a common source voltage may be applied to the common sourceline CSL and the power supply voltage Vcc.

In a second period T2, a second voltage is applied to the word lines WL0to WLn so that the memory cells CA0 to CAn and CB0 to CBk are turned onirrespective of a program state. If the memory cells CA0 to CAn and CB0to CBk are turned on in the state where the drain select transistor DSTis turned on and the ground voltage is applied to the bit lines BL1 andBL2, the ground voltage is applied to the first channel region 313A ofthe first string ST1 and the second channel region 313B of the secondstring ST2.

In a third period T3, the program-inhibited voltage Vpch or the groundvoltage is applied to the bit lines BL1 and BL2 according to externallyinput data. The ground voltage is applied to the first bit line BL1connected to the first string ST1 including the first memory cell CAkthat is to be programmed, and the program-inhibited voltage Vpch isapplied to the second bit line BL2 connected to the second string ST2including the second memory cell CBk (i.e., a program-inhibited cell).The pass voltage Vpass higher than the second voltage is applied to theword lines WL0 to WLn. In the second string ST2, the second channelregion 313B is precharged to a level as much as Vpch-Vth (the thresholdvoltage of the drain select transistor) according to theprogram-inhibited voltage Vpch applied through the second bit line BL2.Since the second channel region 313B is precharged, the drain selecttransistor DST is turned off, so that the second channel region 313Benters a floating state. Further, since a boosting phenomenon isgenerated in response to the pass voltage Vpass, the voltage of thesecond channel region 313B rises. The second voltage applied to the wordlines WL0 to WLn in the second period T2 causes all of the memory cellsCB0 to CBn to turn on, thereby connecting the channel regions 313B ofthe memory cells CB0 to CBn. Accordingly, a boosting phenomenon isgenerated uniformly in the channel regions 313B of the memory cells CB0to CBn according to the pass voltage Vpass irrespective of a programstate.

In a fourth period T4, a program operation is performed by applying theprogram voltage Vpgm to the selected word line WLk. In the first stringST1, electrons are injected from the first channel region 313A to thefloating gate 307 of the memory cell CAk due to the potential betweenthe word line WLk of the memory cell CAk and the first channel region313A, so that the threshold voltage rises. Consequently, the memory cellCAk is programmed.

The program voltage Vpgm is applied in the state where the drain selecttransistor DST of the second string ST2 is turned off and the secondchannel region 313B of the second string ST2 is floated. Thus, aboosting phenomenon occurs additionally in the second channel region313B of the second string ST2 according to the program voltage Vpgm, sothat the voltage of the second channel region 313B rises incidentally.Accordingly, the potential between the word line WLk of theprogram-inhibited cell CBk and the second channel region 313B furtherdecreases. Consequently, the program-inhibited cell CBk is notprogrammed and a program disturbance phenomenon is not generated.

After the program voltage Vpgm is applied for a time sufficient toprogram the memory cell CAk, the supply of the program voltage Vpgm forthe program operation, the pass voltage Vpass, and the drain selectvoltage applied for the drain select line DSL is stopped in theremaining periods. The supply of the voltages may be stoppedsequentially. Though not shown in the drawing, the supply of theprogram-inhibited voltage Vpch and the voltage applied to the commonsource line CSL is also stopped.

After the program operation is performed, a program verificationoperation for verifying whether the threshold voltage of the memory cellCAk has risen to a target voltage is performed. If, as a result of theverification, the threshold voltage of the memory cell CAk has risen tothe target voltage, the program operation is finished. However, if, as aresult of the verification, the threshold voltage has not risen to thetarget voltage, the program operation is performed again according tothe above method while raising the level of the program voltage Vpgmstep-by-step until the threshold voltage becomes the same as or higherthan the target voltage.

The above program method is compared with the prior art below. In theprior art, since the pass voltage or the program voltage is applied inthe state where the channel region within the string is locallyprecharged by the program-inhibited voltage, a boosting phenomenon isgenerated irregularly according to a program state of memory cellswithin the same string. However, in the present invention, since avoltage rises uniformly due to a boosting phenomenon in the wholechannel regions of a string including the program-inhibited cell, theoccurrence of a program disturbance phenomenon can be preventedeffectively.

Although the foregoing description has been made with reference tospecific embodiments, it is to be understood that changes andmodifications of the present invention may be made by one ordinaryskilled in the art without departing from the spirit and scope of thepresent invention and appended claims.

1. A program method of a flash memory device, the program methodcomprising: providing a memory device comprising a drain select line, asource select line, and word lines, and having a string connectedbetween a bit line and a common source line; applying aprogram-inhibited voltage in a state where channel regions within thestring are not electrically connected to the bit line; applying a passvoltage to the word lines; applying a drain select voltage to the drainselect line; and executing a program operation by applying a programvoltage higher than the pass voltage to a selected one of the wordlines.
 2. The program method of claim 1, wherein memory cells that sharethe word lines are turned on according to the pass voltage irrespectiveof a program state.
 3. The program method of claim 1, wherein duringexecution of the program operation, a value of the pass voltage appliedto the selected word line rises to a value of the program voltage. 4.The program method of claim 1, wherein the program-inhibited voltage isapplied before the pass voltage.
 5. The program method of claim 1,wherein the pass voltage is applied before the program-inhibitedvoltage.
 6. The program method of claim 1, wherein the pass voltage andthe program-inhibited voltage are applied at substantially the sametime.
 7. The program method of claim 1, wherein the drain select voltageis applied after the program-inhibited voltage and the pass voltage areapplied.
 8. The program method of claim 1, wherein the drain selectvoltage has substantially the same value as that of theprogram-inhibited voltage.
 9. The program method of claim 1, whereinduring application of the program-inhibited voltage, a source selectvoltage for turning off a source select transistor is applied to thesource select line, and a positive voltage is applied to a common sourceline.
 10. The program method of claim 1, wherein the channel regionswithin the string are disposed in a semiconductor substrate between thesource select line and the drain select line.
 11. The program method ofclaim 1, wherein the channel regions within the string are disposed in asemiconductor substrate under the word lines.
 12. A program method of aflash memory device, the program method comprising: providing a memorydevice comprising a drain select line, a source select line, and wordlines, and having strings respectively connected between bit lines and acommon source line; in a state where channel regions within the stringare not electrically connected to the bit lines, applying a groundvoltage to a first bit line connected to a first string including ato-be programmed memory cell and applying a program-inhibited voltage toa second bit line connected to a second string including aprogram-inhibited cell; applying a pass voltage to the word lines;applying a drain select voltage to the drain select line; and executinga program operation by applying a program voltage higher than the passvoltage to a selected one of the word lines.
 13. The program method ofclaim 12, wherein memory cells that share the word lines are turned onaccording to the pass voltage irrespective of a program state.
 14. Theprogram method of claim 12, wherein during execution of the programoperation, a value of the pass voltage applied to the selected word linerises to a value of the program voltage.
 15. The program method of claim12, wherein a drain select transistor included in the first string isturned on according to the drain select voltage, so that channel regionswithin the first string are electrically connected to the first bitline.
 16. The program method of claim 12, wherein the program-inhibitedvoltage is applied before the pass voltage.
 17. The program method ofclaim 12, wherein the pass voltage is applied before theprogram-inhibited voltage.
 18. The program method of claim 12, whereinthe pass voltage and the program-inhibited voltage are applied atsubstantially the same time.
 19. The program method of claim 12, whereinthe drain select voltage is applied after the program-inhibited voltageand the pass voltage are applied.
 20. The program method of claim 12,wherein the drain select voltage has the same value as that of theprogram-inhibited voltage.
 21. The program method of claim 12, whereinduring application of the program-inhibited voltage, a source selectvoltage for turning off a source select transistor is applied to thesource select line, and a positive voltage is applied to a common sourceline.
 22. The program method of claim 12, wherein the channel regionswithin the string are disposed in a semiconductor substrate between thesource select line and the drain select line.
 23. The program method ofclaim 12, wherein the channel regions within the string are disposed ina semiconductor substrate under the word lines.
 24. A program method ofa flash memory device, the program method comprising: providing a memorydevice comprising a drain select line, a source select line, and wordlines, and having a string connected between a bit line and a commonsource line; applying a program-inhibited voltage to the bit line in afloating state where channel regions within the string are notelectrically connected to the bit line; electrically connecting thechannel regions in a state where the channel regions are notelectrically connected to the bit line; applying a drain select voltageto the drain select line; and executing a program operation by applyinga program voltage higher than a pass voltage to a selected one of theword lines.
 25. The program method of claim 24, wherein the channelregions are connected according to the pass voltage applied to each ofthe word lines.
 26. The program method of claim 25, wherein as thechannel regions are connected according to the pass voltage, a channelboosting phenomenon is generated and a voltage of the channel regionsrises.
 27. The program method of claim 24, wherein the program-inhibitedvoltage is applied before the pass voltage.
 28. The program method ofclaim 24, wherein the pass voltage is applied before theprogram-inhibited voltage.
 29. The program method of claim 24, whereinthe pass voltage and the program-inhibited voltage are applied atsubstantially the same time.
 30. The program method of claim 24, whereinthe drain select voltage is applied after the program-inhibited voltageand the pass voltage are applied.
 31. The program method of claim 24,wherein during application of the program-inhibited voltage, a sourceselect voltage for turning off a source select transistor is applied tothe source select line, and a positive voltage is applied to a commonsource line.
 32. The program method of claim 24, wherein the channelregions within the string are disposed in a semiconductor substratebetween the source select line and the drain select line.
 33. Theprogram method of claim 24, wherein the channel regions within thestring are disposed in a semiconductor substrate under the word lines.34. A program method of a flash memory device, the program methodcomprising: providing a memory device comprising a drain select line, asource select line, and word lines, and having strings respectivelyconnected between bit lines and a common source line; in a floatingstate where channel regions within the string are not electricallyconnected to the bit lines, applying a ground voltage to a first bitline connected to a first string including a to-be programmed memorycell and applying a program-inhibited voltage to a second bit lineconnected to a second string including a program-inhibited cell; in astate where the channel regions are not connected to the bit lines,electrically connecting first channel regions of memory cells, includedin the first string, and second channel regions of memory cells,included in the second string, respectively; in a state where the firstand second channel regions are connected to each other, electricallyconnecting the first channel regions to the first bit line; andexecuting a program operation so that a threshold voltage of the to-beprogrammed memory cell rises.
 35. The program method of claim 34,wherein: the first channel regions are connected to each other accordingto a pass voltage applied to each of the word lines, and the secondchannel regions are connected to each other according to the passvoltage applied to each of the word lines.
 36. The program method ofclaim 35, wherein as a channel boosting phenomenon is generated in eachof the first and second channel regions by the pass voltage, a voltageof the first and second channel regions rises.
 37. The program method ofclaim 34, wherein the first channel regions are connected to the firstbit line as a drain select transistor of the first string is turned onaccording to a drain select voltage applied to the drain select line.38. The program method of claim 34, wherein the drain select voltage hassubstantially the same value as that of the program-inhibited voltage.39. The program method of claim 34, wherein before the first and secondchannel regions are connected to each other, the program-inhibitedvoltage is applied.
 40. The program method of claim 34, wherein afterthe first and second channel regions are connected to each other, theprogram-inhibited voltage is applied.
 41. The program method of claim34, wherein the first and second channel regions are connected to eachother at substantially the same time when the program-inhibited voltageis applied.
 42. The program method of claim 34, wherein after the firstand second channel regions are connected to each other and theprogram-inhibited voltage is applied, the first channel regions areelectrically connected to the first bit line.
 43. The program method ofclaim 34, wherein in the application of the program-inhibited voltage, asource select voltage for turning off a source select transistor isapplied to the source select line, and a positive voltage is applied toa common source line.
 44. The program method of claim 34, wherein thechannel regions within the string are disposed in a semiconductorsubstrate between the source select line and the drain select line. 45.The program method of claim 34, wherein the channel regions within thestring are disposed in a semiconductor substrate under the word lines.46. A program method of a flash memory device, the program methodcomprising: providing a memory device comprising a drain select line, asource select line, and word lines, and having a string connectedbetween a bit line and a common source line; applying a ground voltageto the bit line and a first voltage to the drain select line; applying asecond voltage to the word lines so that memory cells are turned on;applying a pass voltage higher than the second voltage to the word lineswhile applying a program-inhibited voltage to the bit line; andexecuting a program operation by applying a program voltage higher thanthe pass voltage to a selected one of the word lines.
 47. The programmethod of claim 46, wherein the memory cells are turned on according tothe second voltage irrespective of a program state or an erase state.48. The program method of claim 46, wherein during execution of theprogram operation, a value of the pass voltage applied to the selectedword line rises to a value of the program voltage.
 49. The programmethod of claim 46, wherein channel regions within the string areelectrically connected to one another according to the second voltage.50. The program method of claim 49, wherein the channel regions withinthe string are disposed in a semiconductor substrate between the sourceselect line and the drain select line.
 51. The program method of claim50, wherein the channel regions within the string are disposed in asemiconductor substrate under the word lines.
 52. The program method ofclaim 46, wherein during application of the first voltage to the drainselect line, a source select voltage is applied to the source selectline so that a source select transistor is turned off and a positivevoltage is applied to a common source line.
 53. A program method of aflash memory device, the program method comprising: providing a memorydevice comprising a drain select line, a source select line, and wordlines, and having strings respectively connected between bit lines and acommon source line; applying a ground voltage to the bit lines and afirst voltage to the drain select line; applying a second voltage to theword lines so that memory cells are turned on; applying a pass voltagehigher than the second voltage to the word lines, a ground voltage to afirst bit line connected to a first string including a to-be programmedmemory cell, and a program-inhibited voltage to a second bit lineconnected to a second string including a program-inhibited cell; andexecuting a program operation by applying a program voltage higher thanthe pass voltage to a selected one of the word lines.
 54. The programmethod of claim 53, wherein the memory cells are turned on according tothe second voltage irrespective of a program state or an erase state.55. The program method of claim 53, wherein in the execution of theprogram operation, a value of the pass voltage applied to the selectedword line rises to a value of the program voltage.
 56. The programmethod of claim 53, wherein a drain select transistor included in thefirst string is turned on according to the first voltage applied to thedrain select line, so that channel regions within the first string areelectrically connected to the first bit line.
 57. The program method ofclaim 53, wherein channel regions within the string are electricallyconnected to one another according to the second voltage.
 58. Theprogram method of claim 57, wherein the channel regions within thestring are disposed in a semiconductor substrate between the sourceselect line and the drain select line.
 59. The program method of claim58, wherein the channel regions within the string are disposed in asemiconductor substrate under the word lines.
 60. The program method ofclaim 53, wherein during application of the first voltage to the drainselect line, a source select voltage is applied to the source selectline so that a source select transistor is turned off and a positivevoltage is applied to a common source line.
 61. A program method of aflash memory device, the program method comprising: providing a memorydevice comprising a drain select line, a source select line, and wordlines, and having a string connected between a bit line and a commonsource line; applying a ground voltage to the bit line and a firstvoltage to the drain select line; electrically connecting channelregions within the string; generating a channel boosting phenomenon inthe channel regions, thereby raising a potential of the channel regions;and executing a program operation by applying a program voltage to aselected one of the word lines.
 62. The program method of claim 61,wherein the channel regions are connected to one another when memorycells that share the word lines are turned on according to a secondvoltage applied to the word lines.
 63. The program method of claim 61,wherein the potential of the channel regions rises in proportion to avalue in which a voltage applied to the word lines rises as a drainselect transistor that shares the drain select line is turned offaccording to a program-inhibited voltage applied to the bit line and thechannel regions enter a floating state.
 64. The program method of claim61, wherein in the application of the first voltage to the drain selectline, a source select voltage is applied to the source select line sothat a source select transistor is turned off and a positive voltage isapplied to a common source line.
 65. The program method of claim 61,wherein the channel regions within the string are disposed in asemiconductor substrate between the source select line and the drainselect line.
 66. The program method of claim 61, wherein the channelregions within the string are disposed in a semiconductor substrateunder the word lines.
 67. A program method of a flash memory device, theprogram method comprising: providing a memory device comprising a drainselect line, a source select line, and word lines, and having stringsconnected between bit lines and a common source line; applying a groundvoltage to the bit lines and a first voltage to the drain select line;connecting first channel regions of a first string of the strings, whichincludes a to-be programmed memory cell, and second channel regions of asecond string of the strings, which includes a program-inhibited cell;applying a ground voltage to the first channel regions of the firststring and generating a channel boosting phenomenon in the secondchannel regions of the second string, thereby raising a potential of thesecond channel regions; and executing a program operation by applying aprogram voltage to a selected one of the word lines.
 68. The programmethod of claim 67, wherein memory cells that share the word lines areturned on according to a second voltage applied to the word lines, sothat the first channel regions and the second channel regions areconnected to each other.
 69. The program method of claim 68, whereinwhile a drain select transistor of the first string that shares thedrain select line is turned on, the first channel regions areelectrically connected to the first bit line, so that the ground voltageis applied to the first channel regions.
 70. The program method of claim67, wherein the potential of the channel regions rises in proportion toa value in which a voltage applied to the word lines rises as a drainselect transistor of the second string that shares the drain select lineis turned off according to a program-inhibited voltage applied to thesecond bit line and the channel regions become a floating state.
 71. Theprogram method of claim 67, wherein during application of the firstvoltage to the drain select line, a source select voltage is applied tothe source select line so that a source select transistor is turned offand a positive voltage is applied to a common source line.
 72. Theprogram method of claim 67, wherein the channel regions within thestring are disposed in a semiconductor substrate between the sourceselect line and the drain select line.
 73. The program method of claim67, wherein the channel regions within the string are disposed in asemiconductor substrate under the word lines.